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ISL29023
S
S
R
R
SIGNAL FROM
MASTER DEVICE
T
A DEVICE ADDRESS
WRITE
ADDRESS BYTE
T
A DEVICE ADDRESS
READ
DATA BYTE
S
T
O
SIGNAL AT SDA
T
1 0 0 0 1 0 0 0
T
1 0 0 0 1 0 0 1
P
SIGNALS FROM
SLAVE DEVICE
A
C
K
A
C
K
A
C
K
FIGURE 13. BYTE ADDRESS READ SEQUENCE
Read Operation
ISL29023 has two basic read operations: Byte Read and Burst
Read.
BYTE READ
Byte read operations allow the master to access any register
location in the ISL29023. The Byte read operation is a two step
process. The master issues the START condition and the Device
Address byte with the R/W bit set to “0”, receives an
acknowledge, then issues the Register Address byte. After
acknowledging receipt of the register address byte, the master
immediately issues another START condition and the Device
Address byte with the R/W bit set to “1”. This is followed by an
acknowledge from the device and then by the 8-bit data word.
The master terminates the read operation by not responding with
an acknowledge and then issuing a stop condition. Refer to
Figure 13.
BURST READ
Burst read operation is identical to the Byte Read operation.
After the first Data byte is transmitted, the master now responds
with an acknowledge, indicating it requires additional data. The
device continues to output data for each acknowledge received.
The master terminates the read operation by not responding with
an acknowledge but issuing a STOP condition (refer to Figure 14).
For more information about the I 2 C standard, please consult the
Phillips ? I 2 C specification documents.
Power On Reset
The Power-On Reset (POR) circuitry protects the internal logic
against powering up in the incorrect state. The ISL29023 will
power up into Standby mode after VDD exceeds the POR trigger
level and will power down into Reset mode when VDD drops
below the POR trigger level. This bi-directional POR feature
protects the device against ‘brown-out’ failure following a
temporary loss of power.
The POR is an important feature because it prevents the
ISL29023 from starting to operate with insufficient voltage, prior
to stabilization of the internal bandgap. The ISL29023 prevents
communication to its registers and greatly reduces the likelihood
of data corruption on power-up.
S
S
R
R
SIGNAL FROM
MASTER DEVICE
T
A DEVICE ADDRESS
WRITE
ADDRESS BYTE
T
A DEVICE ADDRESS
READ
DATA BYTE 1
DATA BYTE 2
DATA BYTE n
S
T
O
SIGNAL AT SDA
T
1 0 0 0 1 0 0 0
T
1 0 0 0 1 0 0 1
P
SIGNALS FROM
SLAVE DEVICE
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
(“n” is any integer
greater than 1)
FIGURE 14. BURST READ SEQUENCE
7
FN6691.3
April 25, 2013
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